The invention relates generally to automated circuit design, and deals more particularly with a process for designing a circuit using cells each comprised of plural components.
A digital circuit comprises a large number of digital components such as AND gates, OR gates, and Inverters. To fabricate the circuit as an integrated circuit, it is helpful to provide a library of cells that each represent a plurality of the digital components. With such a library, the circuit designer need only select which cells are required to implement the circuit and interconnect the cells, and need not lay-out and interconnect each digital component. Because there are many more individual components than cells, the use of the cells, once designed, substantially reduces the work required to fabricate the integrated circuit.
The larger the cells, the less the work required to lay out and interconnect the entire circuit and the less real estate area required for the entire circuit. However, the larger the cells the greater the tendency for excessive "fan-in" and excessive number of transistors to be in series, and both reduce switching speed.
The design of each cell is a two step process. First, components which make-up each cell are defined, and then the defined components of the cell are layed-out within the cell. For example, the cell may be defined to implement the boolean function (A+B)C+(DE), and then layed-out for the library based on a representation of each OR (+) function by two (or more) FETs in parallel and each AND (no separator) function by two (or more) FETs in series. The boolean inputs are applied to the gates of the respective FETs. There are many known techniques to define and lay-out the cells for the library. For example, "Depth-First Search and Dynamic Programming Algorithm for Efficient CMOSS Cell Generation" by Reuven Bar-Yehuda et al, IEE Transactions on Computer Aided Design, vol. 8. no.7 July 1989 pages 737-743 and "Optimal Cell Generation for Dual Independent Layout Style" by Bradley S. Carlson et al, IEE Transactions on Computer Aided Design, vol. 10, no. 6, June 1991 pages 770-782 describe techniques to define and lay-out the cells. A prior art Yorktown Silicon Compiler also determines and limits the number of series transistors in each component. Nevertheless, these techniques do not adequately consider fan-in and the number of series transistors within each cell.
Accordingly, an object of the present invention is to provide a method and apparatus for automatically designing circuits using cells having limited fan-in and number of transistors in series yet being large enough to be helpful in the fabrication.